The present invention relates to a semiconductor device and a method for fabricating the same, more specifically a semiconductor device including a nonvolatile memory and a method for fabricating the same.
In a semiconductor device including a nonvolatile memory, in addition to flash memory cells, high-voltage transistors for controlling the flash memory, and low-voltage transistors for a high-performance logic circuit are integrated on one semiconductor chip. The flash memory cell has a gate electrode of the stacked structure of a control gate and a floating gate laid the one on the other, which is different from the gate electrodes of the single-layer structure of the high-voltage transistor and the low-voltage transistor. Accordingly, the semiconductor device including the nonvolatile memory has the specific fabrication process that the gate electrodes of the single-layer structure and the gate electrode of the stacked structure are respectively formed by one and the same process.
For example, in fabricating a semiconductor device including a flash memory cell of a fine stacked structure after the 90 nm technology, the depth of trenches formed in the device isolation by STI (Shallow Trench Isolation) must be different between the peripheral circuit region and the flash memory cell region. That is, in the peripheral circuit region, the trenches formed by STI must be deeper to some extent that the insulation between transistors high voltages are applied to is ensured. On the other hand, in the flash memory cell region, the trenches formed by STI must be shallower in comparison with those of the peripheral circuit region so as to prevent defects, as of insufficient filling of the device isolation regions, etc.
A technique of forming trenches by STI, whose depth is different between the peripheral circuit region and the flash memory region, will be the device isolation by STI conducted independently in the peripheral circuit region and the flash memory cell region.
However, high overlay accuracy is required for fine device patterns after, e.g., the 90 nm technology. Accordingly, the device isolation by STI conducted independently in the peripheral circuit region and the flash memory cell region requires unrealistic step administration. It will not be able to meet the requirement of the downsizing of device patterns that the design rules of the peripheral circuits, etc. are mitigated to make the margin for forming patterns larger so as to meet the requirement of the overlay accuracy.
Additionally, high overlay accuracy is required for impurity diffused layers to be formed in the semiconductor substrate. The impurities in such impurity diffused layers are diffused by thermal processing. When the times of the thermal processing are increased as in a case, such as the device isolation by STI is conducted independently in the peripheral circuit region and the flash memory cell region, it is difficult to satisfy the overlay accuracy required for the impurity diffused layers. In this case as well, increasing the margin for forming the patterns cannot meet the requirement of downsizing the device patterns.
A technique for forming trenches of different depths in the device isolation by STI is as exemplified in Reference 1 (Japanese published unexamined patent application No. Hei 7-66276 (1995)).
However, the technique described in Reference 1 has the following disadvantages.
First, a dielectric, such as polysilicon or others, is buried in trenches of different depths formed by STI. Accordingly, it is difficult to ensure the insulation by the device isolation, which is required by a semiconductor device including a flash memory cell. If the technique described in Reference 1 is applied to the device isolation of a semiconductor device including a flash memory cell, required device characteristics will not be able to be obtained.
In one of the techniques described in Reference 1, thermal processing for forming trenches of different depths is frequently conducted, and the diffusion of the impurities in the well is unavoidable. Such diffusion of the impurities is a barrier to downsizing the semiconductor device.
In another one of the techniques described in Reference 1, polysilicon film patterns are formed below an NSG (Non-doped Silicate Glass) film used as a mask for the etching. Steps formed by the absence and presence of the polysilicon film are provided in the mask film. The steps in the mask film are utilized to form trenches of different depths in the silicon substrate. However, it will be very difficult to form the fine patterns, based on the up-and-down steps.
The background arts of the present invention are disclosed in e.g., Japanese published unexamined patent application No. 2002-76148 and Japanese published unexamined patent application No. 2003-289114.